The present invention relates generally to a semiconductor package, and more particularly, to a semiconductor package which uses through-electrodes in such a way as to improve the reliability of an electrical connection within the package.
The semiconductor industry has progressed towards light-weight, high-speed, multi-functional semiconductor products with improved reliability that can be manufactured at a reduced cost. Semiconductor packaging technology is regarded as an important technique for achieving the goals of the semiconductor industry.
Semiconductor packaging technology protects a semiconductor chip (which is formed with a circuit section through a wafer assembly process) from external circumstances; and also, semiconductor packaging technology can be used to easily mount a semiconductor chip to a substrate, thereby securing the operational reliability of the semiconductor chip. Semiconductor packaging technology includes a semiconductor chip attaching process, a wire bonding process, a molding process, and a trimming and forming process. These semiconductor packaging processes can be conducted at the chip level or the wafer level.
Recent efforts in semiconductor packaging technology have been undertaken to develop technologies in which at least two semiconductor chips or semiconductor packages are stacked in order to obtain high capacity of the semiconductor package and to improve mounting efficiency while increasing miniaturization. Through the use of stack packages, a product having greater memory capacity than that attainable using a semiconductor integration process, and a product having higher mounting area utilization efficiency can be obtained.
In stack packages, a semiconductor chip or semiconductor package is electrically connected to a substrate and semiconductor chips or semiconductor packages are electrically connected to each other using metal wires, bumps, or through-electrodes. Using through-electrodes in a stack package to form electrical connections, minimizes the occurrence of electrical degradation. Also, a stack package using through-electrodes for electrical connection can achieve increased operational speed and miniaturization is enabled. The just described benefits are one reason for the recent increase in popularity of stack packages.
The through-electrodes of the stack package are formed by defining via holes in a semiconductor chip and using a plating process to fill the via holes with a metallic material. The through-electrodes may also be formed using a soldering process.
At this time, the through-electrodes (which are formed by the plating or soldering process) and the semiconductor chip have different thermal expansion coefficients. Thus, thermal changes in the semiconductor package are likely to induce cracking in the semiconductor package due to the stress caused by the difference between the respective thermal expansion coefficients, thereby decreasing the semiconductor package's reliability.
When the through-electrodes are formed by defining via holes after a plurality of semiconductor chips or wafers have been stacked, it is difficult to properly form the through-electrodes due to the substantial aspect ratio of the via holes. In other words, when the through-electrodes are formed by the plating process, the substantial aspect ratio of the via holes causes the metallic material forming the through-electrodes to fill in only the upper portions of the via holes. As a consequence, electrical signal connection in the semiconductor package using the through-electrodes becomes impossible. Mechanical experiments show that vapor enters and fills the lower portions of the via holes, resulting in the breakdown of the semiconductor package.